Computer systems capable of handling audio data typically involve encoders and decoders (i.e., “codecs”) capable of converting analog audio data to digital audio data and vice versa. Such codecs generally require digital to analog converters (DACs) and analog to digital converters (ADCs) that operate from reference voltages. For example, a switched capacitor low-pass filter may be used in DACs, which uses reference voltages Vref+ and Vref− as inputs. Such a low-pass filter circuit, as well as further details concerning the context of the use of such circuitry in codecs, is disclosed in U.S. Pat. No. 6,147,522 (“the '522 patent”), which is incorporated herein in its entirety, and with which familiarity is assumed.
A prior art switched capacitor circuit 10 is shown in FIG. 1. Reference inputs Vref+ and Vref− respectively represent filtered versions of power (or Vdd or logic ‘1’) and ground (0V or logic ‘0’), and are fed to the circuit 10 via switches selectively engaged by a one-bit output (Δ) of a well-known delta-sigma modulator (not shown). A one-bit output is only shown for simplicity, and a multi-bit output could be used and normally would be used in a sophisticated real-life codec application.
In the circuit of FIG. 1, the reference voltages propagate through the circuitry using clocks φ1 and φ2 to selectively close various switches (e.g., transistors or pass gates) as shown in the timing diagram of FIG. 1. During φ1, the sampling capacitors Cs, having typical values of approximately 10 picofarads, are charged in accordance with the data Δ. Specifically, the sampling capacitors Cs are charged to Vin-Vcom, where Vin equals Vref+ for one of the sampling capacitors and Vref− for the other sampling capacitor, and where Vcom represents a common mode voltage which can be any value but is typically ½ Vdd. During φ2, the charge stored on the sampling capacitors Cs are coupled in parallel with (and hence share their charge with) integration capacitors C1, which typically measure approximately 100 picofarads. The shared charge is also fed into the differential inputs of operational amplifier (“op amp”) 15, to produce the desired differential analog output, Vout. Providing delayed versions of the clock signals φ1 and φ2 (i.e., φ1d and φ2d) improves this scheme by coupling the charges to and from the various capacitors in an orderly and less noisy fashion, as shown in FIG. 3.
FIG. 1 represents use of the op amp 15 in a differential capacity, with the result being that noise present on Vcom has little to no effect on the output Vout. However, a single-ended architecture is also possible, such as is shown in FIG. 2. This switched capacitor circuit 20 is similar to that disclosed in FIG. 1, but only contains one data path to the op amp 25, with the other input of the op amp being connected to Vcom. While simpler in nature, noise on Vcom in this single-ended scheme directly affects the output voltage, Vout, and so is subject to drawbacks. Although not shown, delayed versions of the clock signals φ1 and φ2 (i.e., φ1d and φ2d as shown in FIG. 3) can be used in the single-ended scheme of FIG. 2 as well, but are not shown for simplicity.
The switched capacitor circuit 40 of FIG. 4, as is disclosed in the above-referenced '522 patent, further improves upon the differential scheme of FIG. 3 by providing two versions of the delayed clock signal (φ1d) responsible for passing data to the plate of the sampling capacitors, Cs. Specifically, the delayed clock signal φ1d is separated into “rough” (φ1dr) and “fine” (φ1df) portions, as shown in the accompanying timing diagram. The rough timing signal φ1dr is used to pass Vdd and ground to the sampling capacitors. This signal passing is both beneficial and detrimental, because while these raw power supply voltages have good drive, they tend to be noisy and unfiltered. However, as these power supply voltages are close in value to Vref+ and Vef−, they are a good starting point for charging the sampling capacitors, Cs, to appropriate values. After this initial charging, the fine timing signal φ1df is used to couple the sampling capacitors to the desired filtered references voltages Vref+ and Vef−. Although not shown, the circuit of FIG. 4 could also be single-ended in nature, similar to the circuit shown in FIG. 2.
Also, in FIG. 4, a capacitor, Cref, which intervenes between the reference voltages Vref+ and Vef−, is shown. Capacitor Cref acts to isolate the reference voltages from one another, and allows voltages Vref+ and Vref− to be passively generated by the circuit as opposed to being actively generated. As it is typically quite large, measuring approximately 10 nanofarads to 10 microfarads, or generally one thousand to one million times bigger than the sampling capacitors, Cref, is typically placed “off chip” from the integrated circuit that includes the switched capacitor circuitry 40 and related electronics (such as the delta sigma modulator etc.). Specifically, capacitor Cref is typically placed on the printed circuit board or other substrate (not shown) to which the integrated circuit is mounted.
Thus, the prior art teaches many different reference voltage circuits and schemes. However, these prior approaches are not optimal. Single-ended schemes such as that disclosed in FIG. 2 are sensitive to noise on voltage Vcom as previously noted. However, differential schemes having differential outputs such as those disclosed in FIGS. 1, 3, and 4 may not be desired by some customers who might want to have to deal with only a single output.
In short, a single-ended scheme not sensitive to noise would be beneficial to the art, and this disclosure presents an example of such an improved scheme.